1. Field of the Invention
The present invention relates to semiconductor integrated circuit apparatus, and in particular to semiconductor integrated circuit apparatus which is capable of controlling a substrate voltage under the low source voltage driving of a miniaturized MOSFET.
2. Description of the Related Art
In recent years, with the advancement of a miniaturization process concerning the fabrication of semiconductor integrated circuit apparatus, the channel length of a MOSFET has come to be fabricated on the order of 0.1 μm or lower. With such process miniaturization, a low voltage of 1 V or less has come to be used as a source voltage and the following reports have been made.
It is reported that, in the environment of a source voltage of 1 V or less, the threshold value and the voltage value of MOSFET are not scaled and the operation speed of a CMOS circuit is inverted in state of low temperatures and high temperatures (refer to Kouichi Kanda and three others, “Design Impact of Positive Temperature Dependence on Drain Current in Sub-1V CMOS VLSIs”, October 2001, IEEE Journal of Solid-State Circuits, vol. 36, No. 10, p. 1559-1564).
It is reported that, for an SRAM as an example of semiconductor integrated circuit apparatus, miniaturization lowers the noise margin thus impairing the stabilized read/write operation from/to the memory cell (refer to Takakuni Douseki and one other Static-Noise Margin Analysis for a Scaled-Down CMOS Memory Cell, Journal of IEICE vol. J75-C-2No. 7, pp. 350-361, July 1992. (In Japanese)).
As a technique to lower the minimum operating voltage under the low source voltage, there is a method for controlling a balance between the source-drain currents of p-type and n-type MOSFETs by way of a substrate bias (refer to Goichi Ono and one other, “Threshold-voltage balance for Minimum Supply Operation”, 2002 IEEE, 2002 Symposium on VLSI Circuit Digest of Technical Papers).
In the aforementioned method (described in Goichi Ono and one other, “Threshold-voltage balance for Minimum Supply Operation”), the delay of an predetermined critical path and a clock cycle is compared, the substrate bias of p-type and n-type MOSFETs is controlled, and the input and output of an inverter comprising a p-type MOSFET and an n-type MOSFET is shorted. With this method, the voltage value of the inverter is compared with the arbitrarily set voltage value of a voltage monitor and correction to offset process variations in the MOSFET so as to stabilize operation with a predetermined voltage.
However, the related art technologies as disclosed in Goichi Ono and one other, “Threshold-voltage balance for Minimum Supply Operation”, 2002 IEEE, 2002 Symposium on VLSI Circuit Digest of Technical Papers do not consider the fact that, in the environment of a source voltage of 1 V or less, the operation speed of a CMOS circuit is inverted at low temperatures and high temperatures described in Kouichi Kanda and three others, “Design Impact of Positive Temperature Dependence on Drain Current in Sub-1V CMOS VLSIS”, October 2001, IEEE Journal of Solid-State Circuits, vol. 36, No. 10, p. 1559-1564 and thus cannot control the substrate voltage of MOSFET to avoid temperature dependence.
The related art low voltage technology (refer to FIG. 9 P/N Vt matching scheme in Goichi Ono and one other, “Threshold-voltage balance for Minimum Supply Operation”, 2002 IEEE, 2002 Symposium on VLSI Circuit Digest of Technical Papers) regulates the Ids of an n-type MOSFET based on a p-type MOSFET, so that it cannot set a subthreshold leakage current or a saturation current to an optimum value.
In other words, according to this method, in semiconductor integrated circuit apparatus incorporating a large-scale memory, stability of operation cannot be enhanced in case the leakage current in the memory reaches several tens to several hundreds of that in other logic circuits.
Or, the method cannot assure the characteristics of the output range of an analog operational amplifier. In circuits such as a dynamic circuit and a domino amplifier as a ore-charged amplifier often used in the timing borrow system, the noise margin is determined by the threshold value of the MOSFET so that it is impossible to supply an optimum threshold value to stabilize the circuit operation.
Assume a configuration where another “scheme” to perform substrate control of a p-type MOSFET is implemented on top of an n-type MOSFET in the same system as Goichi Ono and one other, “Threshold-voltage balance for Minimum Supply Operation”, 2002 IEEE, 2002 Symposium on VLSI Circuit Digest of Technical Papers (see FIG. 9). Assume that semiconductor integrated circuit apparatus whose Ids of the p-type MOSFET is high and the Ids of the n-type MOSFET is low has been fabricate due to process variations.
In this case, the Ids of the p-type MOSFET is high so that the Ids of the n-type MOSFET is low in Goichi Ono and one other, “Threshold-voltage balance for Minimum Supply Operation”, 2002 IEEE, 2002 Symposium on VLSI Circuit Digest of Technical Papers (see FIG. 9). The Ids of the n-type MOSFET is low so that substrate control of the p-type MOSFET is made to decrease the Ids of the p-type MOSFET.
Use of the above system produces a MOSFET having the characteristics opposite to the process variations. In other words, the Ids of the p-type MOSFET is controlled low and the Ids of the n-type MOSFET is controlled high. In this way, even when there are separate circuits which are based on n-type and p-type MOSFETs, it is impossible to optimize the Ids of the p-type and n-type MOSFETs.
The technology of Goichi Ono and one other, “Threshold-voltage balance for Minimum Supply Operation”, 2002 IEEE, 2002 Symposium on VLSI Circuit Digest of Technical Papers (see FIG. 11, SA-Vt CMOS system) is a control method dependent on the delay in a predetermined critical path. This makes it necessary to physically arrange a dummy path circuit corresponding to the predetermined critical path, which increases the area of the semiconductor integrated circuit apparatus.
The technology of the aforesaid non-patent document 3 provides the method for controlling a substrate bias of MOSFET using the delay in the critical path. With such a method, however, in MOSFET devices different in substrate bias dependence within the critical path, such e.g. as devices different in gate oxide thickness or devices different in gate oxide film dielectric constant, in order to match circuit delays with each other, a different substrate voltage cannot be applied to each device different in substrate bias dependence.
In case a large number of critical paths are present under each of the process conditions, temperature conditions and voltage conditions in the semiconductor integrated circuit apparatus and the corresponding logic generator circuits differ from each other, it is necessary to physically arrange a large number of dummy path circuits corresponding to the large number of critical paths, which further increases the area of the semiconductor integrated circuit apparatus.
When a large substrate voltage is applied, the transistor characteristics show the opposite of the regular behavior. On the forward bias side, an excessive forward voltage applied shows bipolar characteristics thus allowing a forward current to flow between the substrate and the drain. The drain-source current is amplified by the substrate voltage. This invalidates the current control across the drain and the source by a gate current.
On the back bias side, an excessive back bias applied generates a GIDL (Gate-Induced Drain Leakage) effect which is an increase in the subthreshold current. In this way, applying an excessive substrate bias inverts the transistor characteristics, causing deadlock to be applied, not feedback.
The bipolar effect is described for example in Tzuen-His Huang et al., “Base Current Reversal Phenomenon in a CMOS Compatible High Gain n-p-n gated Bipolar Transistor”, February 1995, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 2, P 321. The GIDL effect is described for example in Hiroyuki Mizuno and seven others, “An 18-μA Standby Current 1.8-V, 200 MHz Microprocessor with Self-Substrate-Biased Data-Retention Mode”, NOVEMBER 1999, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 11, p. 1392-1500.